Parallel hierarchical global routing for general cell layout
نویسندگان
چکیده
In this paper we present a parallel global routing algorithm for general cell layout. The algorithm applies a hierarchical decomposition strategy that recursively divides routing problems into simple, independent subproblems for parallel processing. The solution of each subproblem is based on integer programming and network flow optimization. The algorithm is implemented on a shared-memory machine and experiment results on different examples show relative speedup between 4 and 5 for 8 processors. The speedup is achieved without compromising the quality of the routing results.
منابع مشابه
Floorplanning with Pin Assignment
We present a hierarchical technique for floorplanning and pin assignment of the general cell layouts. Given a set of cells with their shape lists, a layout aspect ratio, relative positions of the extemal 110 pads and upper bound delay constraints for a set of critical nets, we determine shapes and positions of the cells, locations of the floating pins on cells and a global routing solution such...
متن کاملParallel global routing for standard cells
Combined placement and routing has the potential to achieve better quality automatic layout because the placement optimization can use the actual wire paths to make better decisions. This approach has been considered infeasible because of the computational requirements of the routing task. In this paper, we investigate the potential speedup of a standard cell global router using a general-purpo...
متن کاملA Multiple-objective based Hierarchical Global Routing Approach for VLSI ASIC Design
A VLSI chip can today contain hundreds of millions transistors and is expected to contain more than 1 billion transistors in the next decade. In order to handle this rapid growth in integration technology, the design procedure is therefore divided into a sequence of design steps. Circuit layout is the design step in which a physical realization of a circuit is obtained from its functional descr...
متن کاملHierarchical Pitchmatching Compaction Using Minimum Design
A new hiemrchical compactor capable of compacting and pitchmatching hiemrchically defined layouts is described. The hiemrchrcal compactor can handle most input hiemrchres including multr-level hierarchies, over the cell routing and cell rotations and reflections. The compactor simultaneously compacts the contents of all the cells of the layout hiemrchy maintaining the hierarchy of the input lay...
متن کاملPin assignment with global routing for general cell designs
In this paper, we present an algorithm which combines the pin assignment step and the global routing step in the physical design of VLSI circuits. Our algorithm is based on two key theorems: the channel pin assignment theorem and the block boundary decomposition theorem. These two theorems enable us to deal successfully with the high complexity resulting from combining the pin assignment and gl...
متن کامل